Motivation: As transistor sizes shrink down to the nanoscale, a possible device approach that has attracted large attention recently because of its possibility of enhanced electrostatic control, is the multi-gated nanowire (NW) transistor [1]. Nanowire transistors of diameters even down to 3nm have already been demonstrated by various experimental groups [2-6]. At such small scales, however, the issue of device sensitivity to parameter fluctuations will be critical. Atomistic variations of the side lengths, surface roughness, line edge roughness, cross section shape variations, defects, surface states will exist in these devices and need to be tolerated (if at all possible).

Design Variables in Nanowire Devices

The sensitivity of [110] PMOS nanowire devices to changes in size is a topic of growing research interest. Device orientation, coupled with quantization surfaces, are key design parameters. Previous studies have suggested that [110] and [100] are beneficial transport orientations for NMOS nanowires due to their high current delivery rates. For ballistic PMOS devices, however, simulations have indicated that [100] transport orientation lags behind [110] orientation in current carrying capabilities. The need for advanced device design that can tolerate size variations can't be overstated in this case.

Anisotropic Hole Effective Mass and Device Variations

Analyses of device performance variations usually involve consideration of multiple factors such as interface roughness and phonon scattering. In this work, the focus is on the internal structural and electrostatic quantization behavior of the nanowire. Anisotropy of the hole effective mass underlies these fluctuations and cannot be adequately captured in effective mass models. This additional mechanism could lead to 100% current fluctuations, which significantly exceed the modest current variations of 10-20% typically associated with surface roughness scattering at ON-state.

Atomistic Modelling for Nanowire Devices

Accurately modeling the valence band of Si in the inversion layers (especially for nanowires) is challenging due to the strong non-parabolicity and anisotropy of the heavy-hole and its coupling to the light-hole (LH). As device dimensions shrink drastically, atomistic modeling is necessary to account for crystal symmetry, bond orientation, distortions, surface truncation, and quantum mechanical confinement—all critical features dictating the transport characteristics of nanoscale transistors.

Dispersion and Quantization

It is well recognized that the valence bands of standard semiconductors are extremely anisotropic. The highly anisotropic nature of heavy-hole states in PMOS nanowires make them the dominant ground state in these devices, a fact that will be expounded upon in subsequent semi-analytical explanation of dispersion and quantization. Computed nanowire dispersions include all bands including heavy-, light-hole and split-off.

Valence Band Anisotropy and Quantization Impact

The bulk heavy-hole Si valence band shows significant anisotropy between [100] and [110] directions. The heavier quantization mass along the [1-10] direction makes the valence band edge more sensitive to fluctuations in the shorter [001] side than in the [1-01] side. An examination of [110] nanowire devices reveals that band edge changes are less significant when the width, [1-10], is increased compared to when the height, [001], is increased.

Design and Anisotropy Considerations

By strategically utilizing anisotropic properties in device design, it may be possible to create nanoscale transistors that demonstrate increased tolerance to size variations. Pursuing this line of research could be critical in the progression of nanoscale semiconductor technology, leading to more reliable and efficient devices.